Implementation (Scan, ATPG, MBIST, BSCAN, High speed interface etc.)
Writing test constraints, signing off test mode timing
Verification at various stages, Timing Simulations
Patten generation & tester debug
Production ramp-up
Failure analysis, Yield improvement
Understand DFT architecture of IPs/SoCs
Integrating DFT logic at SoC level
Hands on experience with various DFX/DFT functionalities at IP and SoC level
Exposure to various sanity checks
Build & release to various teams
Interface with PD, Validation & Emulation teams
5 to 10 years of hands on experience with different DFX architectures
Position Responsibility
- ATPG, Understanding/exposure to MBIST, JTAG
- Coverage analysis and improvement for stuck-at, transition fault
- various manufacturing tests (such as voltage droop, voltage monitor, die variation monitors)
- Experience in debugging simulation failures
- Scripting experience
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